This invention relates to integrated circuit memories. More particularly, this invention relates to the timing of data and clock signals of read operations in dynamic random access memories (DRAMs).
A DRAM is a form of semiconductor random access memory (RAM) commonly used as main memory in computers and other electronic systems. DRAMs store information in arrays of integrated circuits that include capacitors. High speed DRAMs, known as synchronous DRAMs (SDRAMs), use clocks to synchronize control and data signal transfers.
SDRAMs often transmit a clock signal along with the data produced from a read request. The clock signal is used by the receiving circuitry to determine when to sample the incoming data. In order to ensure accurate sampling, the data and output clock signals must satisfy certain timing specifications. Two important specifications are t_first and t_last.
The t_first specification defines the time between an output clock edge and the first bit transition on the data bus. This value is restricted to a range greater than a certain value, where the value depends on the size of the output clock period (t_clk). In a double data rate (DDR) system, where data transitions occur on both the rising and falling edges of the output clock, the optimal sampling time is the midpoint between two consecutive clock edges. Therefore, meeting the t_first specification ensures that a data transition occurs sufficiently after a first optimal sampling time.
In contrast, the t_last specification defines the time between an output clock edge and the last bit transition on the data bus. This value is usually restricted to a certain fixed range, e.g., less than 300 picoseconds. Meeting the t_last specification ensures that a data transition occurs sufficiently before a second optimal sampling time.
Assuming a DDR SDRAM system, the ideal timing scenario would have data transitions perfectly time-aligned with the output clock edges. In this ideal case, t_first would be t_clk/2 and t_last would be 0. If the data transitions occurred sufficiently after their corresponding clock edges, the t_first specification would be met, but the t_last specification might be violated. On the other hand, if the data transitions occurred sufficiently before their corresponding clock edges, the t_last specification would be met, but the t_first specification might be violated. Therefore, in a real-world system where some amount of skew is inevitable, meeting both specifications typically involves a tradeoff.
A problem arises when the output clock frequency is increased. As the clock period becomes shorter, meeting the t_first and t_last specifications becomes more difficult. In particular, the physical delay associated with outputting data from an array, referred to as t_delay, often becomes a limiting factor.
Normally, there is a certain latency, referred to as t_lat, involved in memory read operations. t_lat is defined as the amount of time between the start of a read instruction and the first valid edge of the output clock. Typically, t_lat is a certain multiple of the clock period, such as 2*t_clk.
Ideally, t_delay should be less than t_lat, so the outgoing data is latched until the first output clock edge. At that edge, the data is output onto the final data bus, resulting in substantially simultaneous signal transitions. However, if t_delay is greater than t_lat, as can happen when t_clk is very short, the data will be output as soon as it is ready, which can be skewed from the output clock edge by a significant amount. When that happens, it is quite possible to violate either the t_first or the t_last specification, or even both.
In view of the foregoing, it would be desirable to align an output clock with associated data when t_delay is greater than t_lat in order to ensure more reliable compliance with timing specifications. This permits more robust data retrieval and contributes to overall system reliability.